1. Field of the Invention
The present invention relates generally to digital solid state integrated circuits. More particularly, the present invention relates to interfacing circuits implemented using different fabrication processes.
2. Description of Related Art
Interfacing electronic devices which operate on different supply voltages and which necessarily present different input and output characteristics is a problem that has long been known in the art. As digital integrated circuits and the devices which they operate become smaller and smaller, much as in the portable computer market, designers have focused on ways to reduce the size, and also accordingly, the power consumption of each component in a given electronic device. In one particular example, designers have begun to develop digital integrated circuits which operate on 3.3 V references, thereby realizing as much as a 40% power reduction from their predecessors utilizing 5 V references. Because of the advent of digital integrated circuits which operate at 3.3 V, the particular problem of interfacing the input and output characteristics of 3.3 V devices with the more commonly used 5 V devices has presented designers with a wide variety of problems.
In the prior art, designers have typically interfaced 3.3 V devices and 5 V devices by means of an external voltage level translator operated from a 5 V supply. These extemal voltage level translators receive a given 0-3.3 V input signal from a 3.3 V device and adjust the output level so as to present a 0-5 V output level signal to the receiving 5 V device. However, inherent in this extemal translator solution, designers have had to make sacrifices. Performance characteristics, particularly speed and reliability, are reduced in any implementation where the input device must rely on a second device, not able to be located on the same die, for achieving the proper interface voltages. Additionally, more components again take up more space, thereby reducing the gain realized by utilization of 3.3 V devices.
Heretofore, designers have not been able to implement the level transition required at a sending device due to the inherent limitations of the manufactured 3.3 V devices. In order to achieve the size, speed and power consumption goals, a typical BiCMOS fabrication process designed to operate at 3.3 V would have gate oxide thicknesses in the range from 80-150 .ANG. with drawn gate lengths from 0.6-0.8 .mu.m (as compared to a typical 5 V process with gate oxide thicknesses of 150-250 .ANG. and drawn gate lengths greater than or equal to 0.9 .mu.m). While power consumption goals have been achieved, the reduced voltage manufacturing 3.3 V process (hereinafter the 3.3 V process) provides a relatively thin gate oxide and narrow channels that prevent the devices fabricated using a 3.3 V process from being operated at voltages above 3.3 V. At voltages above 3.3 V, hot electron effects and gate oxide breakdown are two of the reliability problems that are well known in the 3.3 V process art.
In the competitive digital integrated circuit market, power consumption, speed, reliability, and compatibility are hallmarks for comparing products produced by different vendors. The ability of a digital integrated circuit to provide an on-chip buffered output for interfacing with more conventional 5 V devices would represent a significant improvement to digital integrated circuit interfhcin g art.